Any of these values may be used by the _ioctl() commands UART_SETCLOCKMODE and UART_GETCLOCKMODE. Most drivers require to set the bit rate after modifying the clock mode. In order to avoid unknown clock output frequencies in master mode, set the clock mode to UART_SYNCSLAVE first, than use UART_SETSPEED to select the bit rate and finally switch to UART_SYNCMASTER or UART_NSYNCMASTER.
Defines | |
#define | UART_ASYNC 0x00 |
Normal asynchronous mode. | |
#define | UART_ASYNC_HS UART_HIGHSPEED |
Asynchronous high speed mode. | |
#define | UART_HIGHSPEED 0x20 |
#define | UART_MASTER 0x02 |
#define | UART_NCLOCK 0x04 |
#define | UART_NSYNCMASTER (UART_SYNC | UART_NCLOCK | UART_MASTER) |
Synchronous master mode, clock negated. | |
#define | UART_NSYNCSLAVE (UART_SYNC | UART_NCLOCK) |
Synchronous slave mode, clock negated. | |
#define | UART_SYNC 0x01 |
#define | UART_SYNCMASTER (UART_SYNC | UART_MASTER) |
Synchronous master mode. | |
#define | UART_SYNCSLAVE UART_SYNC |
Synchronous slave mode. |
#define UART_ASYNC_HS UART_HIGHSPEED |
Asynchronous high speed mode.
More deviation sensitive than normal mode, but supports higher speed.
#define UART_NSYNCMASTER (UART_SYNC | UART_NCLOCK | UART_MASTER) |
Synchronous master mode, clock negated.
Similar to UART_SYNCMASTER, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock output.
#define UART_NSYNCSLAVE (UART_SYNC | UART_NCLOCK) |
Synchronous slave mode, clock negated.
Similar to UART_SYNCSLAVE, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock input.
#define UART_SYNCMASTER (UART_SYNC | UART_MASTER) |
Synchronous master mode.
Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock output.
#define UART_SYNCSLAVE UART_SYNC |
Synchronous slave mode.
Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock input.