XgNutArchArmAt91Ps


PS Control Register

#define PS_CR   (PS_BASE + 0x00)
 Register address.

Peripheral Clock Control Registers

#define PS_PCDR   (PS_BASE + 0x08)
 Peripheral clock disable register address.
#define PS_PCER   (PS_BASE + 0x04)
 Peripheral clock enable register address.
#define PS_PCSR   (PS_BASE + 0x0C)
 Peripheral clock status register address.


Define Documentation

#define PS_CR   (PS_BASE + 0x00)

Register address.

This register allows to stop the CPU clock. The clock is automatically enabled after reset and by any interrupt.


Generated on Tue Jan 23 21:12:30 2007 for BTnut System Software by doxygen 1.4.7