Collaboration diagram for Parallel I/O:
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Most parallel I/O lines are multiplexed with external signals of other peripherals to optimize the use of available package pins.
Defines | |
#define | PIO_BASE |
PIO base address. | |
#define | PIO_PER |
PIO enable register. | |
#define | PIO_PDR |
PIO disable register. | |
#define | PIO_PSR |
PIO status register. | |
#define | PIO_OER |
Output enable register. | |
#define | PIO_ODR |
Output disable register. | |
#define | PIO_OSR |
Output status register. | |
#define | PIO_IFER |
Input filter enable register. | |
#define | PIO_IFDR |
Input filter disable register. | |
#define | PIO_IFSR |
Input filter status register. | |
#define | PIO_SODR |
Set output data register. | |
#define | PIO_CODR |
Clear output data register. | |
#define | PIO_ODSR |
Output data status register. | |
#define | PIO_PDSR |
Pin data status register. | |
#define | PIO_IER |
Interrupt enable register. | |
#define | PIO_IDR |
Interrupt disable register. | |
#define | PIO_IMR |
Interrupt mask register. | |
#define | PIO_ISR |
Interrupt status register. |